1. Field of the Invention
The present invention relates to a semiconductor device, which is suitably used as a device constituting a bipolar LSI, and a manufacturing method thereof.
2. Description of the Related Art
In order to realize a high speed LSI to be used in a mobile communication field or an emitter coupled logic gate array, the development of the technique of a high speed silicon bipolar transistor has been remarkably advanced. In order to improve an operation speed of the bipolar transistor, it is required that a capacitance between a base and a collector and a base resistance be reduced. In order to meet the requirement, there has been proposed a transistor structure in which a collector layer formed by an epitaxial growth technique is surrounded with a device separation region whereby a fine collector region is formed, a base region is formed thereon by a selective epitaxial growth technique, a fine emitter region is formed thereby reducing the capacitance between the base and the collector, and a base lead region is formed beside the base region for a thickness of the base lead region to be thicker than the thickness of the base region thereby reducing the base resistance.
FIG. 1 is a cross sectional view showing such a transistor structure. First, a collector region 51 is formed on a silicon substrate 50 including an n-type buried layer having a high impurity concentration by means of epitaxial growth, and the collector region 51 is insulated and surrounded by a buried oxide layer 52 serving as an element isolation region. Then, a silicon monocrystal region, serving as a base region 53, is formed on only the collector region 51 by a selective epitaxial growth technique.
Next, an insulation film is deposited on the entire surface, and a predetermined patterning is provided thereto, so that an etching stopper film 54 is formed on the base region 53. At this time, since a positioning allowance in a lithography processing and a contact area between an external base lead region and the base region 53 is needed, the etching stopper film 54 is formed to be smaller than the collector region 51, and a distance X1 is needed as shown in FIG. 1.
After that, a polycrystalline silicon layer, serving as a base lead region 55, is deposited, a p-type impurity material is ion-implanted, and an oxide film 56 and a nitride film 57 are sequentially deposited by use of CVD. Thereafter, an opening 58 is formed to form an emitter region. Then, a silicon nitride film is deposited by use of CVD, and a side wall spacer 59 is formed by use of anisotropic etching. The etching stopper film 54 is etched by wet-typed etching without damaging the base region 53, so that an opening 60 is formed.
Thereafter, a polycrystalline silicon layer 61 is deposited, an n-type impurity material is ion-implanted. Then, the impurity material is diffused by thermal treatment, and an emitter region 62 is formed in the base region 53. After that, the polycrystalline silicon layer 61 including the n-type impurity material is patterned to have a predetermined shape. Thereafter, well-known metal electrode forming is performed, so that a transistor is completed.
According to the above-explained manufacturing method, since an extremely thin base layer can be formed, a higher cut-off frequency than that of the transistor having a base layer formed by conventional ion-implantation and diffusion techniques can be obtained.
However, there are problems as set forth below in the above-mentioned structure and manufacturing method thereof.
More specifically, there are needed the distance X1, which is involved in patterning the etching stopper film 54 to be smaller than the collector region 51 serving as an active region of the transistor, and the distance X2, which is involved in estimating a shift of the positioning in the lithography processing for providing the opening 58 for the emitter region. Due to this, the sum of distances X1 and X2 (X1+X2) prevented the structure from being fined. As a result, the capacitance between the base and the collector, and the base resistance, were not sufficiently reduced, and the deterioration of the entire circuit performance was caused. Moreover, in the region just below the emitter, which substantially functions as a transistor, the peripheral portion thereof became large, and a parasitic portion was enlarged.